1) Field of the Invention
The field of invention is electronic design tools and automation, and more specifically methods and systems for facilitating electronic circuit and chip design using resources accessible over a distributed electronic network such as the Internet.
2) Background
The electronics industry produces ever more advanced chip and circuit designs with the assistance of continuously improving design and verification tools. Chip designs may contain tens or hundreds of thousands of gates per chip, and will soon be in the range of millions of gates per chip. Engineers generally require advanced software tools to lay out a chip design and to help manage the huge volume of information associated therewith.
In a high-level view of the electronic design process, a design team takes a product idea from conception to completion over a period of time referred to as “time-to-market.” Increased competition has resulted in immense pressure to reduce time-to-market with new products, because the first company to the market with a new product can typically expect to capture and hold a large market share against later competitors. In this environment, a difference as small as a few days between the planned and the actual shipment of a product may make an enormous difference in its profitability and in the revenue it generates.
In the present environment for designing large scale circuits and complex chips, time and personnel are often short, and budgets are tight. However, design engineers often discover in the middle of the design process that additional tools for automated design and verification are needed, especially if the schedule begins to slip because the team is using tools that are outdated, inadequate for or unsuited to the tasks to be performed, or incompatible with other tools being used. The ability of design engineers to obtain the design tools they need is nevertheless hindered by bureaucratic and cost considerations. Distributors of automated design tools often require purchasers to enter long-term licenses (e.g., 99 years), even though such tools generally have a lifespan of 5 to 10 years before becoming obsolete. Such long-term lease requirements increase design costs and require large capital expenditures by a company. As a result, a long and inefficient purchasing process is typically required in most organizations to purchase such tools. This can lead to delays in obtaining the best tools for the design tasks at hand.
The purchasing process for design and verification tools is inefficient and costly for a variety of reasons. Typically, design engineers have to endure a lengthy internal evaluation and justification procedure for the large capital expenditures involved in obtaining design or verification software. Potential suppliers must be identified and brought in for presentations and demonstrations. Many suppliers perform detailed benchmarks for comparison against one another, and those benchmarks must be evaluated by the responsible members of the design team. Time-consuming supplier negotiations and bureaucratic approval procedures then ensue, before the design team receives authority to order the desired design tool. Despite the slowness of this process, few companies will allow a design team to simply go to a supplier and purchase the tool they want due to the large capital expenditures involved, even though the desired tool is typically the one that is recommended at the end of the evaluation process.
Eventually, when the selection and purchase process has been completed, the design tool must then be installed and tested before use. In the course of this process, weeks or months may be consumed—time that a design team working on a time-critical project can ill afford to waste.
Traditionally, design and verification tools are installed at the end user's site and integrated into the company's existing tool set by an internal computer-aided design (CAD) group whose purpose is to support the engineers. As software tools grow in complexity and diversity, the ability of internal CAD groups to effectively support the most modem design and verification tools diminishes. Further, CAD support personnel are expensive overhead. As a result, an increasing number of companies are choosing not to hire CAD support personnel in order to save money. However, without internal CAD personnel, the individual engineers are left to install and support the tools themselves—a difficult and frustrating proposition that can consume a large number of invaluable working hours.
In addition to high overhead for support personnel, automated design tools also have significant associated hardware costs. Many design and verification programs, particularly simulation programs, require an enormous amount of computing capacity in order to perform their tasks in a reasonable period of time. Thus, after a software tool is selected, additional computer hardware may be required to run it. The need for this additional hardware may not be immediately apparent, causing delays in product development once the need is realized. Further, the design and verification tools may need to be run, albeit critically, for only a few days or weeks, making it potentially inefficient from a capital standpoint to purchase the additional computing power to run such products.
Another drawback with the present way in which design and verification tools are acquired and used relates to technical support. Vendors often have help lines available to users needing technical support for a given software tool. However, assuming that the engineer gets past the frustrating maze of voicemail and one or more layers of less-knowledgeable first-line support personnel which typically characterize vendor help lines, it often takes a long time for the engineer to explain, and for the support personnel to resolve, an issue with a complex tool as applied to a complex circuit. For serious problems, the vendor may send a field applications engineer to the job site, but it is expensive to do so, and several days may pass before a field applications engineer arrives. During that time, the entire design project may remain at a standstill.
A recent trend to increase design speed and efficiency involves the re-use or recycling of electronic circuit blocks or subsystems, which are alternatively referred to as “cores”, “virtual component blocks” or “IPs” (an acronym for “Intellectual Properties,” which denotes the proprietary nature of these pre-packaged circuit blocks). Once the design for a virtual component block has been tested and verified, it can be re-used in other applications which may be completely distinct from the application which led to its original creation. For example, a subsystem for a cellular phone ASIC may contain a micro-controller as well as a digital signal processor and other components. After the design for the cellular phone subsystem has been tested and verified, it could be re-used (as a virtual component block) in, for example, an automotive application. Design reuse of virtual component blocks allows a designer to complete a design much faster than building the entire design from scratch, and avoids the need for debugging, testing and verification of the subsystems embodied in the virtual component block. Examples of virtual circuit blocks or IP cores that are commercially available at present include Viterbi decoders, microcontrollers, digital/analog converters, and encryption/decryption processors, to name a few.
While virtual circuit blocks (i.e., IP cores) provide a means for reducing time-to-market by allowing for the purchase of standard blocks of code, there are a number of barriers to the convenient sale and use of virtual circuit blocks. With regard to quality assurance, for example, there are few, if any, standard methodologies for a designer to be assured of the quality of a virtual circuit block or its suitability for a particular design. Conversely, there are few, if any, standard methodologies for a seller of virtual circuit blocks to demonstrate the quality of the products to prospective customers. Another barrier is protection of the code and/or data comprising the virtual circuit block. Companies providing virtual circuit blocks are in need of a way to track the usage of their products and to protect the code and/or data in those blocks against theft, and such methodologies are preferably unobtrusive, yet allow full access to information required to incorporate those IP cores into a design. Another issue is data format. A virtual circuit block purchased for use in a circuit design must be compatible with the data formats used in that design. However, standards for interfacing with virtual circuit blocks, if they exist, are still evolving. As a result, becoming familiar with an interface format for a virtual circuit block may require a significant amount of work, as well as integrating a virtual circuit block into a circuit design, thus reducing the time advantage obtained through the use of the virtual circuit block. Transaction overhead in the form of high sales and legal costs also discourages sale and use of virtual circuit blocks. For example, legal review by one or both parties is often required with regard to the licensing of virtual circuit blocks.
Component selection is also an area which suffers from inefficiencies and unnecessary time delays. An engineer may consult printed catalogs put out by component distributors to learn about and select parts, or may, using the Internet, visit a website of a supplier of manufacturer, where information about components may be found, or may use a search engine to try to gather product information on the Internet. However, searching the Internet for individual components can be time-consuming and tedious. Further, current search engines and methodologies are inefficient and incomplete, and may thus return search results that do not include websites offering components that a designer could beneficially use in a design. Engineers also may receive unsolicited data sheets from manufacturers, but such data sheets are often discarded, lost or forgotten about. With increasing pressures to decrease time to market, it has become more difficult for engineers to spend time talking to supplier or distributor sales representatives, exacerbating the problem of information gathering about components.
Another problem experienced with the chip design process is that knowledge concerning design and verification processes is fragmented, and it is difficult to capture and maintain such knowledge. Attempting to discern through observation and study the individual design processes of many individual engineers is very challenging. Moreover, the design process can rarely be discerned from final blueprints or products, and is generally difficult to determine from draft or working documents. Different engineers will approach design in different fashions, which they may not even be able to articulate. Interviewing engineers to obtain data about the engineering design process is likely to be unproductive, and to consume a tremendous amount of time for a comparatively small payoff. Thus, benefits in training and improved methodologies that could result from metrics regarding the engineering design process continue to go unrealized.
Some attempts at addressing problems caused by fragmented design and verification processes involve exclusive partnering arrangements among companies that specialize in different areas of the design and verification process, in order to narrow the range of products and services that need to be learned by engineers and supported by internal technical staff. For example, a partnership of electronic design companies may include a provider of design verification tools, a provider of electronic components, and a company that ties them together. In the partnership model, compatibility issues can be addressed more easily, because a limited number of companies are involved. Further, increased revenue is created by influencing a customer of one partner at one phase of the design process to utilize the products or services of another partner in a different phase of the design process. However, a partnering arrangement drastically reduces the choices available to a design team, and may prevent the most optimum product from being used.
One approach for expediting the design process is to provide certain types of design and verification tools—in particular, FPGA synthesis tools—at a remote computer farm that can be accessed over the Internet. Under this approach, the FPGA synthesis tools are run on a central server farm, or computer farm, owned by a single applications service provider. A server farm, or computer farm, is generally a network of processors that are linked together to accomplish higher intensity computing tasks. In an illustrative system utilizing this approach, the applications service provider rewrites the interface of each offered FPGA synthesis tool in the Java® computing language, allowing usage of the tool on a wide variety of computing platforms and operating systems through standard, commercially available Internet browsers. A drawback of this approach is that the user is limited to the FPGA synthesis tools resident in the server farm of the applications service provider for which interface code has been written. Furthermore, the Java® language is notoriously slow, which can frustrate engineers and slow down the design and verification process.
It would be advantageous to connect participants in the electronic design process, including end users and suppliers, through a single portal site that facilitates information exchange and commercial transactions. It would further be advantageous to make a wide variety of design and verification tools readily and conveniently available to design engineers, and to allow use of such tools without a large initial capital outlay in either software or hardware. It would further be advantageous to provide a mechanism for pooling knowledge and information concerning chip design techniques, applications, products and tools. It would also be advantageous to provide a convenient means for allowing engineers to incorporate virtual circuit blocks into their designs.